Advanced wafer-level packaging solutions

High-density integration, high-performance interconnection, and one-stop process services

We provide full-process wafer-level packaging services, covering core processes such as WLCSP packaging, RDL redistribution, and bumping, which can be customized to meet various chip packaging needs

YDCHIP

Product dimensions:Supports processing of 8-inch and 12-inch wafers, enabling u...

Application fields:Smartphone camera chips, sensor chips, power management chips, RF chips, etc

Detailed Introduction

Product Overview

Wafer-level packaging (WLP) is an advanced packaging technology that directly encapsulates and tests the entire wafer after its manufacturing is completed, eliminating the need for traditional lead frames and substrates, significantly reducing the package size and thickness. Our company boasts a complete wafer-level packaging production line and a seasoned technical team, offering a one-stop solution from design simulation, process development to mass production, which is widely applied in consumer electronics, automotive electronics, IoT, communications, and other fields.

Technical Characteristics

Supports processing of full-size wafers of 4/6/8/12 inches

The minimum line width/line spacing can reach 2μm/2μm (RDL process)

The minimum supported bump pitch is 50μm, and bumps made of various materials such as copper pillars, tin-silver, and gold can be fabricated

Supports multi-layer RDL stacking and fan-out packaging technology

Possessing high-precision lithography, electroplating, bonding, and cutting process capabilities

Compatible with various chip types such as CMOS, MEMS, sensors, etc

Electrical / Thermal Performance

The parasitic inductance of the packaging is reduced by over 60%, significantly enhancing signal transmission speed and integrity

The packaged resistor is reduced by 50%, resulting in lower power consumption and heat generation

With a thermal resistance as low as 1.2℃/W, it boasts excellent heat dissipation performance

Supports high-frequency applications, up to 40GHz

Excellent electromagnetic interference (EMI) resistance

earliest delivery time

Sample making: fastest 7-10 working days

Small batch trial production: fastest 15-20 working days

Mass production: Negotiated based on order quantity, typically 30-45 working days

Expedited service is available, and the delivery time can be further shortened

Minimum Order Quantity (MOQ)

Sample stage: minimum order quantity of 1 wafer

Small batch trial production: minimum order quantity of 5 wafers

Mass production: minimum order quantity of 50 wafers

Special customization requirements can be negotiated to adjust the minimum order quantity

Product Type

Wafer-level Chip-scale Package (WLCSP)

Fan-in WLCSP

Fan-out WLCSP

Ultra-thin WLCSP (thickness < 0.3mm)

Redistribution Layer (RDL) process

Single-layer / Multi-layer RDL fabrication

High-density RDL wiring

Embedded passive component RDL

Bumping process

Copper pillar bump (Cu Pillar)

Solder bumps (SnAg, SnPb)

Gold Bump

Micro Bump

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