A comprehensive explanation of the SIP packaging process for UDICore, with fully transparent testing steps!

1. About UDIC Semiconductor

Youdi Core Semiconductor, a wholly-owned subsidiary of Yixinwei Semiconductor Technology (Shenzhen) Co., Ltd., is situated in the Zhongcheng Biomedical Industrial Park in Pingshan District, Shenzhen. It is recognized as a national high-tech enterprise and a national-level specialized, refined, unique, and innovative enterprise. The company specializes in R&D, packaging, testing, and module integration services, integrating storage solution development, advanced packaging and testing, module assembly testing and services, as well as brand operations.

The company boasts 1,500 square meters of Class 1000 and 5,000 square meters of Class 10,000 purification workshops, equipped with industry-leading advanced packaging and testing equipment, and possesses full-process production capabilities from wafer testing to finished product shipment. Its products are widely used in various fields such as consumer electronics, industrial control, automotive electronics, and medical equipment, providing customers with high-quality and high-reliability packaging and testing solutions.

II. Detailed Explanation of the Full Process Flow of UD-Core SiP Packaging

SiP (System-in-Package) is an advanced technology that integrates multiple functional chips (such as processors, memories, RF chips, etc.), passive components (resistors, capacitors, inductors), as well as MEMS and optical devices, into a single package. With years of technical accumulation, UDIC has established a mature and efficient SiP packaging process:

Phase 1: Preliminary preparation and wafer-level processing

Incoming wafer inspection: Conduct comprehensive visual inspection and electrical testing on wafers provided by customers to ensure that the wafer quality meets packaging requirements

Wafer thinning: Using Chemical Mechanical Polishing (CMP) technology to reduce the wafer thickness from its original thickness to 100-200μm, meeting the demand for thinner packaging

Wafer cutting: Using a high-precision laser cutting machine to cut the wafer into individual chips (dies), with a cutting accuracy of up to ±5μm

Chip selection: Qualified chips are screened out and defective chips are eliminated through automatic optical inspection (AOI) equipment

Phase 2: Substrate preparation and chip mounting

Incoming substrate inspection: Conduct comprehensive inspections on the appearance, dimensions, and electrical performance of the packaging substrates

Substrate pretreatment: Clean and bake the substrate to remove surface impurities and moisture

Chip bonding: Qualified chips are precisely bonded to designated positions on the substrate using a high-precision mounter, achieving a bonding accuracy of ±10μm

Curing: Fully cure the adhesive by heating to ensure a firm bond between the chip and the substrate

Stage 3: Interconnection and packaging

Wire Bonding: Using gold wires, with the assistance of high temperature and ultrasonic energy, to electrically connect chip pads with corresponding terminals on the substrate, achieving a bonding strength of over 10g

Flip Chip: For high-performance chips, flip chip technology is employed to achieve direct connection between the chip and the substrate through solder bumps, significantly reducing signal delay

Plasma cleaning: removes contaminants generated during the bonding process, enhancing the adhesion of subsequent plastic encapsulation

Molding: In a clean room environment, the semi-finished product is placed in a heated mold, and thermosetting epoxy resin is injected. After being pressurized and heated, it cures to form a protective encapsulation

Post-curing: Conduct post-curing treatment in a high-temperature oven to ensure complete crosslinking of the epoxy resin, thereby enhancing the mechanical strength and heat resistance of the encapsulation

Stage 4: Post-processing and testing

Marking: Utilizing laser marking technology to imprint product model, batch number, production date, and other relevant information onto the surface of the packaging

Solder ball implantation: Implant solder balls at the bottom of the package to prepare for subsequent surface mounting

Reflow soldering: Through reflow soldering, solder balls are firmly bonded to the package body

Singulation: Cutting the entire encapsulated board into individual, independent SiP devices

Comprehensive testing: Conducting multiple rounds of testing, including appearance inspection, electrical performance testing, and reliability testing

Packaging and Shipping: Vacuum-pack qualified products to ensure quality and safety during transportation and storage

III. Fully transparent testing process: the core of quality control

Udix has always regarded product quality as the lifeline of the enterprise, and has established a strict testing system covering the entire process to ensure that every SiP device leaving the factory meets the highest quality standards. The company promises full transparency in the testing process, and customers can view test data and reports at any time.

Pre-packaging testing: controlling quality from the source

Wafer testing (CP testing): Using probe cards to conduct 100% electrical testing on the entire wafer, screening out defective chips to avoid subsequent packaging waste

Chip appearance inspection: Using high-power microscopes and automatic optical inspection equipment, inspect chips for defects such as scratches, cracks, and chipped corners

Testing in packaging: process quality monitoring

Bonding strength test: Randomly select samples for bonding strength testing to ensure the secure and reliable connection between the gold wire and the chip as well as the substrate

X-ray inspection: Through X-ray fluoroscopy, the internal structure of the package is examined to detect defects such as broken or shorted gold wires, as well as voids or delamination in the plastic encapsulation

Shear force test: Test the bonding strength between the chip and the substrate to ensure that the chip does not fall off during use

Post-packaging testing: final quality control

Appearance final inspection: Conduct a 100% inspection of the appearance of SiP devices, including whether the package body has scratches or deformations, and whether the solder balls are missing or offset

Electrical performance testing (FT testing): Utilize automated test equipment (ATE) to conduct comprehensive electrical performance testing on each device, encompassing DC parameters, AC parameters, functional testing, and more

High and low temperature testing: Conduct cyclic testing within the temperature range of -40℃ to +125℃ to verify the operational stability of the device under extreme temperature conditions

Burn-in test: Conduct a long-duration power-on test on devices under high temperature and high pressure conditions to screen out early failures

System-level testing (SLT testing): Installing SiP devices into actual application systems for testing, simulating real usage scenarios, and ensuring normal system-level functionality

IV. Technical Advantages and Service Commitments

Udix has multiple core technological advantages in the field of SiP packaging:

Supports multi-chip heterogeneous integration, capable of integrating chips of different processes and materials

Possess high-precision surface mounting capabilities for ultra-thin passive components and multiple heterogeneous chips

Equipped with advanced electromagnetic shielding technology, it effectively addresses electromagnetic interference issues arising from high-density integration

Provide one-stop services from packaging design, simulation, manufacturing to testing

The company promises to its customers:

7x24-hour technical support, with rapid response to customer needs

48-hour sample delivery, shortening the customer's product development cycle

Having completed both IECQ and RoHS international registrations simultaneously, the product can be directly exported

Provide detailed test reports and data to ensure full transparency in the testing process

We can coordinate with customers to directly ship the packaged finished products to overseas production lines, reducing intermediate links